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1 ? fn8162.4 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005, 2008. all rights reserved all other trademarks mentioned are the property of their respective owners x9119 single supply/low power/1024-tap/2-wire bus single digitally-controlled (xdcp?) potentiometer the x9119 integrates a single digitally controlled potentiometer (xdcp?) on a m onolithic cmos integrated circuit. the digital controlled potentiometer is implemented using 1023 resistive elements in a series array. between each element are tap points connected to the wiper terminal through switches. the position of the wiper on the array is controlled by the user through t he 2-wire bus interface. the potentiometer has associated with it a volatile wiper counter register (wcr) and a four non-volatile data registers that can be directly written to and read by the user. the contents of the wcr controls the position of the wiper on the resistor array though the switches. powerup recalls the contents of the default data register (dr0) to the wcr. the xdcp? can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. features ? 1024 resistor taps ? 10-bit resolution ? 2-wire serial interfac e for write, read, and transfer operations of the potentiometer ? wiper resistance, 40 typical @ v cc = 5v ? four non-volatile data registers ? non-volatile storage of multiple wiper positions ? power-on recall. loads saved wiper position on power-up. ? standby current < 3a max ?v cc : 2.7v to 5.5v operation ?100k end-to-end resistance ? 100 yr. data retention ? endurance: 100,000 data changes per bit per register ? 14 ld tssop ? low power cmos ? single supply version of the x9118 ? pb-free available (rohs compliant) functional diagram r h r l bus r w interface control pot v cc v ss 2-wire bus address data status write read wiper 1024-taps transfer nc nc 100k power-on recall wiper counter register (wcr) data registers (dr0-dr3) control interface and data sheet july 9, 2008
2 fn8162.4 july 9, 2008 detailed functional diagram ordering information part number part marking v cc limits (v) potentiometer organization (k ) temp range (c) package p k g. d w g. # x9119tv14i x9119 tvi 5 10% 100 -40 to +85 14 ld tssop (4.4mm) m14.173 x9119tv14iz (note) x9119 tvzi -40 to +85 14 ld tssop (4.4mm) (pb-free) m14.173 x9119tv14 x9119 tv 0 to +70 14 ld tssop (4.4mm) m14.173 x9119tv14z (note) x9119 tvz 0 to +70 14 ld tssop (4.4mm) (pb-free) m14.173 x9119tv14-2.7* x9119 tvf 2.7 to 5.5 0 to +70 14 ld tssop (4.4mm) m14.173 x9119tv14z-2.7* (note) x9119 tvzf 0 to +70 14 ld tssop (4.4mm) (pb-free) m14.173 x9119tv14i-2.7 x9119 tvg -40 to +85 14 ld tssop (4.4mm) m14.173 x9119tv14iz-2.7* (note) x9119 tvzg -40 to +85 14 ld tssop (4.4mm) (pb-free) m14.173 *add "t1" suffix for tape and reel. please refer to tb347 for details on reel specifications. note: these intersil pb-free plastic packaged products employ special pb-free materi al sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb a nd pb-free soldering operations). intersil pb-free products are msl cl assified at pb-free peak reflow temperatures that meet or ex ceed the pb-free requirements of ipc/jedec j std-020. scl a1 sda a2 wp interface and control circuitry v cc v ss dr0 dr1 dr2 dr3 wiper counter register (wcr) r h r l data r w 1024-taps 100k control power on recall a0 x9119
3 fn8162.4 july 9, 2008 applications circuit level ? vary the gain of a voltage amplifier ? provide programmable dc reference voltages for comparators and detectors ? control the volume in audio circuits ? trim out the offset voltage error in a voltage amplifier circuit ? set the output voltag e of a voltage regulator ? trim the resistance in wheatstone bridge circuits ? control the gain, characteristic frequency and q-factor in filter circuits ? set the scale factor and zero point in sensor signal conditioning circuits ? vary the frequency and duty cycle of timer ics ? vary the dc biasing of a pin diode attenuator in rf circuits ? provide a control variable (i, v, or r) in feedback circuits system level ? adjust the contrast in lcd displays ? control the power level of led transmitters in communication systems ? set and regulate the dc biasing point in an rf power amplifier in wireless systems ? control the gain in audio and home entertainment systems ? provide the variable dc bias for tuners in rf wireless systems ? set the operating points in temperature control systems ? control the operating point for sensors in industrial systems ? trim offset and gain errors in artificial intelligent systems pinout x9119 (14 ld tssop) top view bus interface pins serial data input/output (sda) the sda is a bidirectional serial data input/output pin for a 2-wire slave device and is used to transfer data into and out of the device. it receives device address, opcode, wiper register address and data sent from an 2-wire master at the rising edge of the serial clock scl, and it shifts out data after each falling edge of the serial clock scl. it is an open drain output and may be wire-ored with any number of open drain or open collector outputs. an open drain output requires the use of a pull-up resistor. for selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. serial clock (scl) this input is used by 2-wire master to supply 2-wire serial clock to the x9119. device address (a 2 ?a 0 ) the address inputs are used to set the least significant 3 bits of the 8-bit slave address. a match in the slave address serial data stream must be made with the address input in order to initiate communication with the x9119. a maximum of 8 devices may occupy the 2-wire serial bus. hardware write protect input (wp ) the wp pin when low prevents nonvolatile writes to the data registers. potentiometer pins r h , r l the r h and r l pins are equivalent to the terminal connections on a mechanical potentiometer. v cc r l v ss 1 2 3 4 5 6 7 8 14 13 12 11 10 9 nc r w a2 a1 r h a0 nc sda nc scl wp pin assignments pin number pin name function 1, 3, 10 nc no connect 2 a0 device address for 2-wire bus 4 a2 device address for 2-wire bus 5 scl serial clock for 2-wire bus 6 sda serial data input/output for 2-wire bus 7v ss system ground 8wp hardware write protect 9 a1 device address for 2-wire bus 11 r w wiper terminal of the potentiometer 12 r h high terminal of the potentiometer 13 r l low terminal of the potentiometer 14 v cc system supply voltage x9119
4 fn8162.4 july 9, 2008 r w the wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. bias supply pins system supply voltage (v cc ) and supply ground (v ss ) the v cc pin is the system supply voltage. the v ss pin is the system ground. other pins no connect no connect pins should be left open. these pins are used for intersil manufacturing and testing purposes. principals of operation the x9119 is an integrated mi crocircuit incorporating a resistor array and its associ ated registers and counters and the serial interface logic providing direct communication between the host and the digita lly controlled potentiometer. this section provides detail description of the following: ? resistor array description ? serial interface description ? instruction and register description resistor array description the x9119 is comprised of a resistor array. the array contains, in effect, 1023 discrete resistive segments that are connected in series (figure 1). the physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (r h and r l inputs). at both ends of each array and between each resistor segment is a cmos switch connected to the wiper (r w ) output. within each individual array only one switch may be turned on at a time. these switches are controlled by the wiper counter register (wcr). the 10-bits of the wcr (wcr[9:0]) are decoded to select, and enable, one of 1024 switches. the wcr may be written directly. the data registers and the wcr can be read and written by the host system. serial interface description serial interface the x9119 supports a bidirectional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master will always initiate data transfers and prov ide the clock for both transmit and receive operations. therefore, the x9119 will be considered a slave device in all applications. clock and data conventions data states on the sda line can change only during scl low periods. sda state changes during scl high are reserved for indicating start and stop conditions (figure 3). start condition all commands to the x9119 are preceded by the start condition, which is a high to low transition of sda while scl is high. the x9119 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition is met (figure 3). serial data path from interface register 0 serial bus input parallel bus input counter register r h r l r w 10 10 c o u n t e r d e c o d e if wcr = 000[hex] then r w = r l if wcr = 3ff[hex] then r w = r h wiper (wcr) (dr0) circuitry register 1 (dr1) register 2 (dr2) register 3 (dr3) figure 1. detailed potentiometer blo ck diagram serial interface description r x9119
5 fn8162.4 july 9, 2008 stop condition all communications must be terminated by a stop condition, which is a low to high transition of sda while scl is high (see figure 3). acknowledge acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. the transmitting device, either t he master or the slave, will release the sda bus after transmitting eight bits. the master generates a ninth clock cycle and during this period the receiver pulls the sda line low to acknowledge that it successfully received the eight bits of data. the x9119 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful rece ipt of the command byte. if the command is followed by a data byte the x9119 will respond with a final acknowledge (see figure 2). acknowledge polling the disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical 5ms eeprom write cycle time. on ce the stop condition is issued to indicate the end of the nonvolatile write command the x9119 initiates the intern al write cycle. ack polling, flow 1, can be initiated immedi ately. this involves issuing the start condition followed by the device slave address. if the x9119 is still busy with t he write operation, no ack will be returned. if the x9119 has completed the write operation, an ack will be returned and the master can then proceed with the next operation. flow 1. ack polling sequence scl from master data output from transmitter 1 89 st ar t ackno wledge data output from receiver figure 2. acknowledge response from receiver nonvolatile write command completed enterack polling issue start issue slave address ack returned? further operation? issue instruction issue stop no yes yes proceed issue stop no proceed x9119
6 fn8162.4 july 9, 2008 instruction and register description device addressing: identification byte (id and a) following a start condition, th e master must output the address of the slave it is accessing. the most significant four bits of the slave address are the device type identifier. the id[3:0] bits is the device id for the x9119; this is fixed as 0101[b] (refer to table 1). the a2?a0 bits in the id byte is the internal slave address. the physical device address is defined by the state of the a2?a0 input pins. the slave address is externally specified by the user. the x9119 compares the serial data stream with the address input state; a su ccessful compare of both address bits is required for the x9119 to successfully continue the command sequenc e. only the device which slave address matches the incoming device address sent by the master executes the inst ruction. the a2?a0 inputs can be actively driven by cmos input signals or tied to v cc or v ss . the r/w bit is the lsb and is be used to program the device for read or write operations. instruction byte and register selection the next byte sent to the x91 19 contains the instruction and register pointer information. the three most significant bits are used provide the instruction opcode (iop[2:0]). the rb and ra bits point to one of the four registers. the format is shown below in table 2. table 3 provides a complete summary of the instruction set opcodes. table 1. identification byte format table 2. instruction byte format table 3. instruction set note: 1/0 = data is one or zero. id3 id2 id1 id0 a2 a1 a0 r/w 0101 (msb) (lsb) device type identifies internal slave address read or write bit i2 i1 i0 0 rb ra 0 0 (msb) (lsb) instruction opcode register selection register selected rb ra dr0 0 0 dr1 0 1 dr2 1 0 dr3 1 1 instruction instruction set operation r/w i 2 i 1 i 0 0rbra 0 0 read wiper counter register 1 1 0 0 0 0 0 0 0 read the contents of the wiper counter register write wiper counter register 0 1 0 1 0 0 0 0 0 write new value to the wiper counter register read data register 1 1 0 1 0 1/0 1/0 0 0 read the contents of the data register pointed to rb-ra. write data register 0 1 1 0 0 1/0 1/0 0 0 write new value to the data register pointed to rb-ra. xfr data register to wiper counter register 1 1 1 0 0 1/0 1/0 0 0 transfer the contents of the data register pointed to by rb-ra.to the wiper counter register xfr wiper counter register to data register 0 1 1 1 0 1/0 1/0 0 0 transfer the contents of the wiper counter register to the data register pointed to by rb-ra. x9119
7 fn8162.4 july 9, 2008 instruction and register description device addressing wiper counter register (wcr) the x9119 contains a wiper counter registers (refer to table 4) for the xdcp potentiometer. the wcr is equivalent to a serial-in, parallel-out register/counter with its outputs decoded to select one of 1024 switches along its resistor array. the contents of the wcr can be altered in one of three ways: 1. it may be written directly by the host via the write wiper counter register instruction (serial load) 2. it may be written indirectly by transferring the contents of one of four associated data registers via the xfr data register 3. it is loaded with the contents of its data register zero (r0) upon power-up. the wiper counter register is a volatile register; that is, its contents are lost when the x9119 is powered-down. although the register is autom atically loaded with the value in dr0 upon power-up, this may be different from the value present at power-down. power-up guidelines are recommended to ensure proper loadings of the dr0 value into the wcr. data registers (dr0 to dr3) the potentiometer has four 10-bit non-volatile data registers. these can be read or written directly by the host. data can also be transferred between any of the four data registers and the wiper counter register. all operations changing data in one of the data registers is a nonvolatile operation and will take a maximum of 10ms. if the application does not r equire storage of multiple settings for the potentiometer, the data registers can be used as regular memory locati ons for system parameters or user preference data. bit 9?bit 0 are used to store one of the 1024 wiper position (0 ~1023). table 4. wiper control register, wcr (10-bit), wcr9?wcr0: used to store the current wiper position (volatile, v) table 5. data register, dr (10-bit), bit 9?bit 0: used to store wiper positions or data (non-volatile, nv) four of the six instructions are four bytes in length. these instructions are: ? read wiper counter register ? read the current wiper position of the selected potentiometer, ? write wiper counter register ? change current wiper position of the selected potentiometer, ? read data register ? read the contents of the selected data register; ? write data register ? write a new value to the selected data register. the basic sequence of the four by te instructions is illustrated in figure 3. these four-byte instructions exchange data between the wcr and one of t he data registers. a transfer from a data register to a wcr is essentially a write to a static ram, with the static ram cont rolling the wiper position. the response of the wiper to this action will be delayed by t wrl . a transfer from the wcr (current wiper position), to a data register is a write-to-nonv olatile memory and takes a minimum of t wr to complete. the transfer can occur between one of the four pot entiometers and one of its associated registers. two instructions (figure 4) require a two-byte sequence to complete. these instru ctions transfer data between the host and the x9119; either between the host and one of the data registers or directly between the host and the wiper counter register. these instructions are: ? xfr data register to wiper counter register ? this transfers the contents of one specified data register to the wiper counter register. ? xfr wiper counter register to data register ? this transfers the contents of the wiper counter register to the specified data register. see ?instruction format? on page 8 for more details. power-up and down requirements there are no restrictions on the power-up condition of v cc and the voltages applied to the potentiometer pins provided that the v cc is always more positive than or equal to the voltages at r h , r l , and r w , i.e. v cc r h , r l , r w . there are no restrictions on the power-down condition. however, the datasheet parameters for the dcp do not apply until 1ms after v cc reaches its final value. wcr9 wcr8 wcr7 wcr6 wcr5 wcr4 wcr3 wcr2 wcr1 wcr0 vvvvvvvvvv (msb) (lsb) bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 nv nv nv nv nv nv nv nv nv nv msb lsb x9119
8 fn8162.4 july 9, 2008 instruction format read wiper counter register (wcr) write wiper counter register (wcr) read data register (dr) s t a r t 01 01 a2 a1 a0 r/w a c k i2 i1 i0 0 rb ra 0 a c k scl sda s t o p 000 id3 id2 id1 id0 device id internal instruction opcode address register address figure 3. two-byte instruction sequence s t a r t a c k a c k scl sda a c k s t o p a c k id3 id2 id1 id0 a2 a1 a0 r/w i2 0 00 x x0 0 xxx w c r 9 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 i1 i0 0 rb ra 0 101 xx x device id internal address instruction opcode register address wiper or data position figure 4. four-byte instruction sequence (w rite or read for wcr or data registers) w c r 8 w c r 7 w c r 6 w c r 5 s t a r t device type identifier device addresses s a c k instruction opcode register addresses s a c k wiper position (sent by slave on sda) m a c k wiper position (sent by slave on sda) m a c k s t o p 0101a2a1a0 r / w = 1 10000000 xxxxxx w c r 9 w c r 8 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 s t a r t device type identifier device addresses s a c k instruction opcode register addresses s a c k wiper position (sent by master on sda) s a c k wiper position (sent by master on sda) s a c k s t o p 0101a2a1a0 r / w = 0 1010 0000 xxxxxx w c r 9 w c r 8 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 s t a r t device type identifier device addresses s a c k instruction opcode register addresses s a c k wiper position (sent by slave on sda) m a c k wiper position or data (sent by slave on sda) m a c k s t o p 0 1 0 1 a2 a1 a0 r / w = 1 1 0 1 0rbra0 0 xxxxxx w c r 9 w c r 8 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 x9119
9 fn8162.4 july 9, 2008 write data register (dr) transfer wiper counter register (wcr) to data register (dr) transfer data register (dr) to wiper counter register (wcr) notes: 1. a2 ~ a0?: stand for the device addresses sent by the master. 2. wcrx refers to wiper position data in the wiper counter register s t a r t device type identifier device addresses s a c k instruction opcode register addresses s a c k wiper position or data (sent by master on sda) s a c k wiper position or data (sent by master on sda) s a c k s t o p high-voltage write cycle 0 1 0 1 a2 a1 a0 r / w = 0 1100rbra00 xxxxxx w c r 9 w c r 8 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 s t a r t device type identifier device addresses s a c k instruction opcode register addresses s a c k s t o p high-voltage write cycle 0101a2 1 a0 r / w = 0 1110rbra00 s t a r t device type identifier device addresses s a c k instruction opcode register addresses s a c k s t o p 0101a2a1a0 r / w = 1 1100rbra00 x9119
10 fn8162.4 july 9, 2008 notes: 1. absolute linearity is utilized to determine actual wiper volt age vs expected voltage as determi ned by wiper position when use d as a potentiometer. 2. relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. it is a measure of the error in step size. 3. mi = r tot /1023 or (r h ? r l )/1023, single pot 4. n = 0, 1, 2, ?,1023; m =0, 1, 2, ?, 1022. 5. esd rating on r h , r l , r w pins is 1.5kv (hbm, 1.0a leakage maximu m), esd rating on all other pins is 2.0kv. absolute maxi mum ratings voltage on scl, sda, or any address input with respect to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to +7v v = | (vh?vl) |. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5v i w (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma operating conditions commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to +85c supply voltage (vcc) limits (note 4) x9119 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v 10% x9119-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v thermal information temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65c to +135c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c lead temperature (soldering, 10s). . . . . . . . . . . . . . . . . . . . . . 300 c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. analog specifications (over recommended operation conditions unless otherwise stated.) parameter symbol test conditions min (note 8) typ max (note 8) units end-to-end resistance r total 100 k end-to-end resistance tolerance 20 % power rating +25c, each pot 50 mw wiper current i w 3 ma wiper resistance r w wiper current = 50a, v cc = 5v 40 110 wiper current = 50a, v cc = 3v 150 300 voltage on any r h or r l pin v term v ss = 0v v ss 5v noise ref: 1v -120 dbv resolution 0.1 % absolute linearity (note 1) r w(n)(actual) ? r w(n)(expected) , where n = 8 to 1006 1 mi (note 3) r w(n)(actual) ? r w(n)(expected) (note 4) 1.5 2.0 mi (note 3) relative linearity (note 2) r w(m + 1) ? [r w(m) + mi], where m = 8 to 1006 0.5 mi (note 3) r w(m + 1) ? [r w(m) + mi] (note 4) 0.5 1.0 mi (note 3) temperature coefficient of r total 300 ppm/c ratiometric temp. coefficient 20 ppm/c potentiometer capacitancies c h /c l /c w see macro model 10/10/25 pf x9119
11 fn8162.4 july 9, 2008 capacitance notes: 6. limits should be considered typi cal and are not production tested. 7. t pur and t puw are the delays required from the time the (last) power supply (vcc-) is stable until the specific instruction can be issued. t hese parameters are not 100% tested. 8. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. operating specifications (over the recommended operating conditions unless otherwise specified.) parameter symbol test conditions min. typ. max. units v cc supply current (active) i cc1 f scl = 400khz; v cc = +5.5v; sda = open; (for 2-wire, active, read and volatile write states only) 3ma v cc supply current (nonvolatile write) i cc2 f scl = 400khz; v cc = +5.5v; sda = open; (for 2-wire, active, non-volatile write state only) 5ma v cc current (standby) i sb v cc = +5.5v; v in = v ss or v cc ; sda = v cc ; (for 2-wire, standby state only) 3a input leakage current i li v in = v ss to v cc 10 a output leakage current i lo v out = v ss to v cc 10 a input high voltage v ih v cc x 0.7 v cc + 1 v input low voltage v il -1 v cc x 0.3 v output low voltage v ol i ol = 3ma 0.4 v output high voltage v oh endurance and data retention parameter min units minimum endurance 100,000 data changes per bit per register data retention 100 years test symbol max units test conditions input/output capacitance (si) c in/out (note 6) 8 pf v out = 0v input capacitance (scl, wp , a1 and a0) c in (note 6) 6 pf v in = 0v power-up timing parameter symbol min max units v cc power-up rate t r v cc (note 6) 0.2 50 v/ms power-up to initiation of read operation t pur (note 7) 1 ms power-up to initiation of write operation t puw (note 7) 50 ms ac test conditions i nput pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 x9119
12 fn8162.4 july 9, 2008 equivalent a.c. load circuit r h 10pf c l c l r w r total c w 25pf 10pf r l spice macromodel 5v 1533 100pf sda output 3v 867 100pf sda output ac timing high-voltage write cycle timing parameter symbol min max units clock frequency f scl 400 khz clock cycle time t cyc 2500 ns clock high time t high 600 ns clock low time t low 1300 ns start setup time t su:sta 600 ns start hold time t hd:sta 600 ns stop setup time t su:sto 600 ns sda data input setup time t su:dat 100 ns sda data input hold time t hd:dat 0ns scl and sda rise time t r 300 ns scl and sda fall time t f 300 ns scl low to sda data output valid time t aa 250 ns sda data output hold time t dh 0ns noise suppression time constant at scl and sda inputs t i 50 ns bus free time (prior to any transmission) t buf 1300 ns a0, a1, a2 setup time t su:wpa 0ns a0, a1, a2 hold time t hd:wpa 0ns high-voltage write cycle timing parameter symbol typ max units high-voltage write cycletime (store instructions) t wr 510ms xdcp timing parameter symbol min max units wiper response time after thethird (last) power supply is stable t wrpo 510s wiperresponse time after instruction issued (all load instructions) t wrl 510s x9119
13 fn8162.4 july 9, 2008 symbol table timing diagrams start and stop timing input timing output timing waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance t su:sta t hd:sta t su:sto scl sda t r ( start) (stop) t f t r t f scl sda t high t low t cyc t hd:dat t su:dat t buf scl sda t dh t aa x9119
14 fn8162.4 july 9, 2008 xdcp timing (for all load instructions) write protect and device address pins timing scl sda r w (stop) lsb t wrl sda scl ... ... ... wp a0, a1, a2 t su:wpa t hd:wpa (start) (stop) (any instruction) x9119
15 fn8162.4 july 9, 2008 applications information basic configurations of electronic potentiometers application circuits v r rw +v r i three terminal potentiometer; variable voltage divider two terminal variable resistor; variable current noninverting amplifier voltage regulator offset voltage adjustment c omparator with hysteresis + ? v s v o r 2 r 1 v o = (1+r 2 /r 1 )v s r 1 r 2 i adj v o (reg) = 1.25v (1+r 2 /r 1 )+i adj r 2 v o (reg) v in 317 + ? v s v o r 2 r 1 v ul = {r 1 /(r 1 +r 2 )} v o (max) rl l = {r 1 /(r 1 +r 2 )} v o (min) 100k 10k 10k 10k -12v +12v tl072 + ? v s v o r 2 r 1 } } x9119
16 fn8162.4 july 9, 2008 application circuits (continued) attenuator filter inverting amplifier equivalent l-r circuit + ? v s v o r 3 r 1 v o = g v s -1/2 g +1/2 g o = 1 + r 2 /r 1 fc = 1/(2prc) + ? v s v o r 2 r 1 z in = r 2 + s r 2 (r 1 + r 3 ) c 1 = r 2 + s leq (r 1 + r 3 ) >> r 2 + ? v s function generator r 2 r 4 r 1 = r 2 = r 3 = r 4 = 10k + ? v s r 2 r 1 r c } } v o = g v s g = - r 2 /r 1 r 2 c 1 r 1 r 3 z in + ? r 2 + ? r 1 } } r a r b frequency r 1 , r 2 , c amplitude r a , r b c v o x9119
17 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8162.4 july 9, 2008 x9119 thin shrink small outlin e plastic packages (tssop) index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-153-ac, issue e. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dam bar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimen- sion at maximum material conditi on. minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. (angles in degrees) 0.05(0.002) m14.173 14 lead thin shrink small outline plastic package symbol inches millimeters notes min max min max a - 0.047 - 1.20 - a1 0.002 0.006 0.05 0.15 - a2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - d 0.195 0.199 4.95 5.05 3 e1 0.169 0.177 4.30 4.50 4 e 0.026 bsc 0.65 bsc - e 0.246 0.256 6.25 6.50 - l 0.0177 0.0295 0.45 0.75 6 n14 147 0 o 8 o 0 o 8 o - rev. 2 4/06

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